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SIS3700 32-bit ECL input FIFO


The SIS3700 is a receiver board for ECL or LVDS data streams with a width of up to 32-bits. The card is optimised for the acquisition of FERA and PCOS data streams. Various end conditions, like timeout e.g., are implemented. Data can be read out through VME or a P2 row A/C cable bus in parallel to the acquisition of new data, as decoupling is handled by the on board FIFO chips.





  • 32-bit ECL input (LVDS option available)
  • 40 MB/s input rate
  • Event structure
  • Different end of event conditions
  • 1K deep event and data FIFO (4K/16K/64K available on request)
  • 16-bit pack mode
  • VME access, user LED and 4 status LEDs
  • A24/A32/D32/BLT32 slave interface
  • P2 A/C local bus readout capability
  • VME FIFO test capability
  • VME64x Connectors
  • VME64x Side Shielding
  • Single +5V supply


Simplified block diagram:



Application examples:

  • PCOS/FERA readout (dual ported memory replacement)
  • Serialized pixel/strip detector readout